DTCO
DIRECT COATING INC
stock OTC

As the hyper-scalers load up on debt and seeing reduction in free operating cash flow, the idea of cost savings is bound to come up.
And when management conversation touches that topic, the technical people in the group will ask how can we reduce the margins earn by our supply chain providers by going direct to the source.
To design there is the EDA software layer (EDA players are like Cadence and Synopsis) before doing up the hardware silicon (mostly going to TSMC)
So the foundry or design companies provide their IPs, Cell Libraries (e.g. 18A or 18AP | High Density or High Performance), design rules to those EDA players for integration and designing up the SOC requirements.
Running simulations and fine tuning the voltage, frequency, critical path and temperature etc.
Henceforth it's important to get on good terms with EDA. And Lip Bu was ex-cadence, so hopefully he can leverage his connections there.
I can see a path where Intel integrate itself (assuming the foundry side can deliver), then it makes more sense for external customers to tap on Intel services (both ASIC and Foundry).
For Design Technology Co-Optimziation (DTCO) -> Fabs
Over at Fabs, silicon fabrication and then advanced packaging.
Also includes product testing and validation (over at Intel Malaysia Penang)
Or chiplet framework
where chiplet A over TSMC and chiplet B at Intel then advanced packaging (CoWos or EMIB).
So Intel can still or at least have >50% of earning something from it. As long as it's a good ROI rate.
That's quite substantial cost savings, which is what the Meta and Hyper-Scalers need right now. Since the margins paid to providers like Broadcom, Marvell & Mediatek and finally to TSMC, can be trimmed from two layers to just 1 (direct to Intel).
**Doesn't matter where you pay (division level: Intel DCG or Intel Foundry) as long as it's to Intel we'll set aside resources to cover that account.**
That's how Lip Bu should view it.

As the hyper-scalers load up on debt and seeing reduction in free operating cash flow, the idea of cost savings is bound to come up.
And when management conversation touches that topic, the technical people in the group will ask how can we reduce the margins earn by our supply chain providers by going direct to the source.
To design there is the EDA software layer (EDA players are like Cadence and Synopsis) before doing up the hardware silicon (mostly going to TSMC)
So the foundry or design companies provide their IPs, Cell Libraries (e.g. 18A or 18AP | High Density or High Performance), design rules to those EDA players for integration and designing up the SOC requirements.
Running simulations and fine tuning the voltage, frequency, critical path and temperature etc.
Henceforth it's important to get on good terms with EDA. And Lip Bu was ex-cadence, so hopefully he can leverage his connections there.
I can see a path where Intel integrate itself (assuming the foundry side can deliver), then it makes more sense for external customers to tap on Intel services (both ASIC and Foundry).
For Design Technology Co-Optimziation (DTCO) -> Fabs
Over at Fabs, silicon fabrication and then advanced packaging.
Also includes product testing and validation (over at Intel Malaysia Penang)
Or chiplet framework
where chiplet A over TSMC and chiplet B at Intel then advanced packaging (CoWos or EMIB).
So Intel can still or at least have >50% of earning something from it. As long as it's a good ROI rate.
That's quite substantial cost savings, which is what the Meta and Hyper-Scalers need right now. Since the margins paid to providers like Broadcom, Marvell & Mediatek and finally to TSMC, can be trimmed from two layers to just 1 (direct to Intel).
**Doesn't matter where you pay (division level: Intel DCG or Intel Foundry) as long as it's to Intel we'll set aside resources to cover that account.**
That's how Lip Bu should view it.