ARM
Arm Holdings plc
stock NASDAQ ADR

ARM and Tesla are the only two high-multiple stocks in my portfolio. The market has priced them at extreme valuations because it anticipates massive long-term earnings growth a thesis I agree with. However, because their valuations rely so heavily on distant future cash flows rather than near-term profits, they are naturally the most volatile holdings I own.

Hey! Fascinating results. I'm relatively new to low-latency architecture, so I'm trying to calibrate some of my own hobby numbers against what you're seeing here.
I've been experimenting with a tiny dependency-free C11 SPSC ring-buffer implementation using fixed-stride slots and index passing rather than copying the payload.
On a commodity AMD EPYC 7763 cloud instance, using POSIX shared memory rather than DPDK or any hardware bypass, I get roughly:
64B serialized RTT

min 0.242 us
p10 0.558 us
p50 0.599 us
p90 0.673 us
p99 0.816 us
p99.9 1.290 us
avg 0.615 us
That's an actual round trip through the producer/consumer path, so under reasonably symmetric conditions the corresponding one-way component would be in the \~300 ns range, although I wouldn't equate RTT/2 directly with transport latency. But those numbers are when threads are not cpu core pinned and without removing the specified cores from the OS completely (isolcpus=0,1 ) without disabling the hardware interrupts for those cores (nohz\_full=0,1) and so on). In fact I'm aiming for dual digits nanosec RTT in the ringbuff.
Under streaming workloads with 4 KB frames I'm getting \~5.95M msg/s and \~23.2 GB/s mem troughput.
So seeing your kernel-backed DPDK/veth path at **1.74 µs p50 / 3.26 µs p99** for 62-byte frames is particularly interesting. It makes me wonder where the dominant cost is appearing in that path - veth/kernel traversal, AF\_PACKET, DPDK PMD interaction, scheduling/cache effects, or simply the different timestamp boundaries.
That also got me thinking about pushing the same architecture in the opposite direction.
I have a cheap e-waste Antminer controller board with a Xilinx Zynq SoC. Instead of PCIe + DMA, the idea would be to put the SPSC index/ring mechanism directly into dual-port BRAM: FPGA fabric parses the incoming stream and writes normalized market fields into fixed offsets, while the ARM side consumes the slots through the second BRAM port.
Reason while I'm trying this approach is potentially replacing a much larger PCIe/DMA/software transport path with a very deterministic few-cycle hardware/software handoff.
For someone who has actually built FPGA-assisted HFT/data-plane systems: is this architecture fundamentally sound, or am I underestimating the ugly parts of doing line-rate parsing and buffering on a small Zynq?
In particular, I'm wondering where you'd expect the real bottleneck to appear first: parser state/clock rate, BRAM bandwidth, AXI latency, ARM cache/coherency, or simply getting deterministic Ethernet ingress/egress timing.
The fun part is that the same tiny SPSC/index-shuffling abstraction should survive almost unchanged; only the producer side moves from software into FPGA fabric.

Yes. ARM, SPCX and RKLB. And it’s expensive for good reasons.
You want cheap go buy Nike, McDonald’s 😪

It's a nice rate! My ARM hovered around down there for way more years than I ever expected it too!

ARM and Tesla are the only two high-multiple stocks in my portfolio. The market has priced them at extreme valuations because it anticipates massive long-term earnings growth a thesis I agree with. However, because their valuations rely so heavily on distant future cash flows rather than near-term profits, they are naturally the most volatile holdings I own.

Hey! Fascinating results. I'm relatively new to low-latency architecture, so I'm trying to calibrate some of my own hobby numbers against what you're seeing here.
I've been experimenting with a tiny dependency-free C11 SPSC ring-buffer implementation using fixed-stride slots and index passing rather than copying the payload.
On a commodity AMD EPYC 7763 cloud instance, using POSIX shared memory rather than DPDK or any hardware bypass, I get roughly:
64B serialized RTT

min 0.242 us
p10 0.558 us
p50 0.599 us
p90 0.673 us
p99 0.816 us
p99.9 1.290 us
avg 0.615 us
That's an actual round trip through the producer/consumer path, so under reasonably symmetric conditions the corresponding one-way component would be in the \~300 ns range, although I wouldn't equate RTT/2 directly with transport latency. But those numbers are when threads are not cpu core pinned and without removing the specified cores from the OS completely (isolcpus=0,1 ) without disabling the hardware interrupts for those cores (nohz\_full=0,1) and so on). In fact I'm aiming for dual digits nanosec RTT in the ringbuff.
Under streaming workloads with 4 KB frames I'm getting \~5.95M msg/s and \~23.2 GB/s mem troughput.
So seeing your kernel-backed DPDK/veth path at **1.74 µs p50 / 3.26 µs p99** for 62-byte frames is particularly interesting. It makes me wonder where the dominant cost is appearing in that path - veth/kernel traversal, AF\_PACKET, DPDK PMD interaction, scheduling/cache effects, or simply the different timestamp boundaries.
That also got me thinking about pushing the same architecture in the opposite direction.
I have a cheap e-waste Antminer controller board with a Xilinx Zynq SoC. Instead of PCIe + DMA, the idea would be to put the SPSC index/ring mechanism directly into dual-port BRAM: FPGA fabric parses the incoming stream and writes normalized market fields into fixed offsets, while the ARM side consumes the slots through the second BRAM port.
Reason while I'm trying this approach is potentially replacing a much larger PCIe/DMA/software transport path with a very deterministic few-cycle hardware/software handoff.
For someone who has actually built FPGA-assisted HFT/data-plane systems: is this architecture fundamentally sound, or am I underestimating the ugly parts of doing line-rate parsing and buffering on a small Zynq?
In particular, I'm wondering where you'd expect the real bottleneck to appear first: parser state/clock rate, BRAM bandwidth, AXI latency, ARM cache/coherency, or simply getting deterministic Ethernet ingress/egress timing.
The fun part is that the same tiny SPSC/index-shuffling abstraction should survive almost unchanged; only the producer side moves from software into FPGA fabric.

Yes. ARM, SPCX and RKLB. And it’s expensive for good reasons.
You want cheap go buy Nike, McDonald’s 😪

It's a nice rate! My ARM hovered around down there for way more years than I ever expected it too!

I never thought I would be wrong about an ARM in 2025.

ARM for me, honestly. Bought a tiny position I can't justify on fundamentals because I like the IP moat and figured a small stake beats staring at the chart with regret for a decade (kind of how I feel keeping dubious piece activity on the board instead of simplifying, sometimes "I like it" wins over "the computer line says trade it off"). Costco's the one that gets me the most though, never once looked cheap and never seems to matter.
fwiw I don't actually trade, just watch SPY and this stuff from the sidelines, so take the position-sizing talk with a grain of salt.

I would love to own ARM.  I think 2027 is perfectly setup for ARM to dominate.  It is just so hard to justify 122 forward 

100+ and that was irrelevant because of Xilinx acquisition. Acquisition cost was amortized for 5 years as an accounting trick.
Back to ARM - I also like the company, but won't touch it as long as Softbank is playing with them. Very high risk of pump n dump. Pledging shares to create/ squeeze supply of floating shares in the market. I'd just be very careful 

I agree it isn't intuitive.
But I've done a lot of math on my own scenario around this exact question. And all the math I've done on this (with my actual mortgage and investment numbers) indicates that I end up with more money if I don't pay off the house.
Different people's situations will certainly vary.
But basically money tied up in your asset (paid off home) does not draw interest. Every dollar you pay towards your principal is a dollar that will not earn interest for you.
Investing instead leads to compound interest.
Interest on a mortgage does not compound - it's set at the time of signing (unless you have an ARM or make some bad decisions along the way).
So at the end of 30 years, you can have a paid-for house and a 15 year old portfolio. Or you can have a paid-for house and a 30 year portfolio.
Yes, you got to invest more after paying off the mortgage. But with a 15 year headstart, the compound interest wins in every scenario I've tested.
There is absolutely an emotional benefit and peace of mind from paying off the mortgage early. But if it comes at the cost of my portfolio being insufficient to sustain me in my retirement, then I might end up with a new mortgage anyway. And I would feel pretty silly about paying it off early only to tie up that capital, earn 0% interest on it, and then have to pull it back out anyway.

if you have an ARM, you're either a flipper or you don't care about your finances.

$ARM valuation gives me aids

ARM BABY ARM 🥰🥰🥰

Stay away from ARM at these prices. You have nvidia at 1/5 of the valuation and higher growth.

$ARM

ARM is the most over valued company in this game. It’s leveraged like anything by Softbank which owns 90% of it and it’s volatile as hell. Please look into financials.
You have much better opportunities like AVGO.

I'm tempted to do this with ARM. I'm drawn to this company for several reasons, from its business and AI potential to what looks like a great culture judging by employee reviews on Glassdoor.
The problem is that even under optimistic assumptions, I struggle to see attractive returns from today's price.
Yet I still find myself wanting to own it.
Anyone else have a company like this? Have you bought shares despite your valuation concerns, perhaps keeping the position small, or do you always wait for a price you can justify?